The present invention relates to the transfer of data, for example the transmission of multiple data messages over a single transmission medium and the conversion of those messages into a form suitable for transmission.
There is a growing market in the field of digital communication. An increasing number of households have equipment to receive digital television, satellite and cable television, telephony and internet services. Telephony systems and the internet are interactive systems over which people can send and receive information and other digital communication systems are increasingly tending towards interactivity, for example as video-on-demand systems are introduced.
Video, audio and other information (e.g. internet services), all hereinafter referred to as xe2x80x9cdataxe2x80x9d, can be transmitted along a number of transmission media, for example over electrical or optical cable or via radio. The data can be considered to be made up of xe2x80x9cmessagesxe2x80x9d, each message being, for example, one television channel or one internet connection. To allow a plurality of messages to be sent over a single transmission channel one approach is to split the messages into parts at the transmission device, transmit each part over the transmission channel and then recombine the parts at the receiving device to reconstitute the message. Each message is thus contained in a number of parts, which can arrive at the receiving device over a period of time. Additional information can be transmitted with each segment, for example to indicate the message of which the segment forms part. Consecutively sent messages need not then form part of the same message since the receiving device can use the additional information to allow it to recombine segments of each message with each other.
One system that uses this principle is AAL5. In this system data is transmitted in the form of asynchronous transfer mode (ATM) xe2x80x9ccellsxe2x80x9d of 53 bytes in length, of which the first 5 bytes constitute the additional information mentioned above and the other 48 bytes constitute the segment of the message. By convention each byte consists of 8 bits.
The messages themselves may be split into higher-level parts before they reach the transmission stage: for example video data can be in the form of MPEG frames.
One practical embodiment of a personal system for handling data in this form is a set-top box. This usually receives a digital data feed, forms the received data into digital messages, performs the necessary digital-to-analogue conversion and final backend processing of the messages and outputs signals suitable for use by other apparatus such as televisions, telephones or internet terminals. There is also normally provision for transmission of information (normally at a lower data rate) in the opposite direction to allow a user to operate interactive services. The reverse data can conveniently, although not necessarily be sent in the same format as the forward data.
In order to meet the demands of consumers for high data rate services such as video a set-top box should preferably be capable of receiving and transmitting at a rate of at least 1 to 10 Mbits/s and preferably of receiving at least 50 Mbits/s. This imposes very heavy demands on the processing systems that are to perform the transmitting and receiving operations, especially the segmentation of messages into parts and the reassembly of those parts. Since the set-top box is intended as a consumer product there is a particular need to provide a device for performing the transmitting and receiving operations that is as inexpensive as possible.
There are known integrated circuit systems that can perform the segmentation and re-assembly (xe2x80x9cSARxe2x80x9d) functions described above for use in a personal system. Current systems fall generally into two categories, having the following characteristics:
Hardware-based designs
Very fast dedicated SAR engines (typically 155/622 Mbits/s)
Large silicon areas
Expensive, and although they are hardware-based systems they often still require a microprocessor for control purposes
Complicated control registers and memory management data structures defined in hardware
Inflexible, which makes it difficult to adapt them to rapidly evolving new standards and markets
Software/Processor-based designs
Relatively slow (usually sub 20 Mbits/s)
Can be inexpensive with cheap RISC (reduced instruction set computing) processors, but become uneconomic in embedded situations at high data rates (40-50 Mbits/s upwards) because expensive high performance processors are needed
Flexible, as all control and data structures are software-defined, so easier to modify as standards evolve
In fact, there are four conflicting design requirements which need to be met for widespread consumer use:
Cost Targets. To a large extent the cost of an integrated circuit SAR engine is determined by the complexity of the circuit and the die area it occupies. Known hardware-based systems generally occupy large areas and whilst low-cost RISC software-based systems are cheaper to produce, their performance is modest.
Flexibility to meet evolving standards. Hardware-based systems are generally inflexible.
Performance targets. Existing hardware-based solutions have high performance but are too expensive for many consumer applications. Existing software-based solutions are cheaper but have modest performance.
Ease of Interfacing to other parts of the system
It is clear from the above analysis that the SAR engines currently available do not provide an effective technical and cost-effective solution.
According to a first aspect of the present invention there is provided a data reception apparatus for receiving data from a plurality of data streams sent over a data channel, the apparatus comprising:
a data memory for storing the received data;
a data storage control memory for storing, for each data stream, a definition of a corresponding storage block in the data memory, the storage blocks for the respective data streams being capable of being of different lengths;
a data storer for identifying in the data received on the data channel amounts of data and the data stream from which each amount of data is sent, accessing the storage control memory to determine the storage block corresponding to the said data stream, storing that amount of data in the storage block corresponding to the said data stream and, if no more amounts of data can be stored in that storage block, generating a block full indication for that block; and
a memory controller responsive to a block full indication for a storage block to allocate to the data stream corresponding to that storage block another storage block in the data memory by storing, for that data stream, a definition of the other storage block in the data storage control memory.
Preferably the data storer is provided by dedicated circuitry on an integrated circuit. Preferably the memory controller is provided by the central processing unit of an integrated circuit. Preferably the data storer and the memory controller are provided by separate processing circuitry on a single integrated circuit.
At least part of the data memory is preferably on the integrated circuit. The integrated circuit may include memory.
At least some of the storage blocks are preferably contiguous sets of memory locations. At least some of the blocks may alternatively not be contiguous.
Preferably the storage block comprises an end memory address and the length of the storage block. Preferably the storage blocks are of differing sizes. Preferably the differing sizes of the storage blocks are programmable under software control by the central processing unit and/or dynamically changeable during operation of the apparatus.
The data storage control memory preferably stores error check information for at least one of the data streams and on receiving an amount of data from that data stream the data storer performs an error check calculation using the stored error check information and the contents of the amount of data to calculate second error check information and stores the second error check information in the data control memory to replace the first error check information.
The data storer preferably generates the block full indication after receiving an amount of data that can not be stored in the storage block. Preferably if the data storer determines that an amount of data can not be stored in the storage block and that that amount of data is a final amount of data of a message it generates a block full indication of a second type, in response to which the memory controller allocates a smaller storage block for the data stream.
The memory controller preferably maintains a list of storage blocks available for allocation.
The data storage control memory preferably stores for each data stream an indication of a location in the data memory at which the data storer is to store the next-received amount of data for that data stream.
The data memory is preferably provided by at least two discrete memory units.
Each amount of data is preferably received in the form of an ATM cell. The amount of data is suitably 384 bits.
According to a second aspect of the present invention there is provided a method for receiving a plurality of data streams over a data channel, the method comprising performing the steps set out above in relation to the first aspect of the invention.
The present invention will now be described by way of example with reference to the accompanying drawings in which: